Impact of 3D IC on NoC Topologies: A Wire Delay Consideration

International audienceIn this paper, we perform an exploration of 3D NoC architectures through physical design implementation based on two tiers Tezzaron 3D technology. The 3D NoC partitioning is done by dividing the NoC's datapath component into two blocks placed in the two tiers. Two Stacked NoC architectures namely Stacked 3D-Mesh NoC and Stacked 2D-Hexagonal NoC developed based on this partitioning strategy are analyzed by comparing their performances with Stacked 2D-Mesh NoC and classical 2D- Mesh and 3D-Mesh NoC. In order to measure the impact of wire delay on performance, two technology libraries (130 nm and 45 nm) representing old and advanced technologies have been used for the performance analysis. Results from physical implementations show that in advanced technologies such as 45 nm and below, the performance of Stacked 2D NoC topologies with datapath partitioning method have better performances compared with traditional 2D/3D Mesh topologies and Stacked 3D Mesh topology. We advocate here that with stacking there is no need for 3D NoC topologies for advanced 2-tier 3D IC and this is also confirmed for multistage networks like butterfly

BinDCT Design and Implementation on FPGA with Low Power Architecture

Image compression is widely used in today's consumer applications such as digital camcorders, digital cameras, videophones and high-definition television (HDTV). As Discrete Cosine Transform (DCT) is dominant in many international standards for image/video and audio compression, the introduction of multiplierless algorithm for fast DCT computation known as BinDCT (Binary DCT) is very well suited for VLSI implementation. Its performances in term of Peak Signal-to-Noise (PSNR), compression ratio and coding gain is proved to be best approximation to the DCT algorithm. In this work, the design and implementation of 8 x 8 block 2-D forward BinDCT algorithm on a Field Programmable Gate Array (FPGA) is presented. As this algorithm uses simple arithmetic operations (shift and add) rather than floating-point multiplications, low power hardware implementation is very promising. The aim for low power implementation was achieved at architectural level by employing 4 stages pipeline architecture with parallel processing in each stage. However, due to the trade off between hardware area and speed, this design is focusing on optimising hardware area in each stage such that it can fit the target FPGA device. The 8 x 8 block two-dimensional (2-D) forward BinDCT implementation can be run at 68.58 MHz with the power consumption of 144.10 mW. This implementation achieved 12.45% less power compare with the implementation of BinDCT presented previously if the design runs at the same speed. Furthermore, results have shown that this implementation achieved good accuracy compare with software implementation as the maximum error of the output from 2-D computation is 1.26 %. Several works can be done for further power optimisation such as data gating and latency balancing at each stage (which can improves the throughput as well). Besides, the implementation of 8 x 8 block 2-D inverse BinDCT should be carried out such that its accuracy over floating-point DCT in terms of hardware implementation can be analyzed

3D MPSoC Design Using 2D EDA tools: Analysis of Parameters

International audienceDesign space exploration of 3D MPSoC architecture is reported in this paper analyzing the impact of 2D EDA tools to the 3D architecture performance. In particular, we study how 3D performance is varied when changing the EDA tools options intending to highlight design issues of 3D design. Results show that 3D timing performance is affected greatly compared with power consumption and total wirelength

FPGA IMPLEMENTATION OF ZIEGLER-NICHOLS CLOSED-LOOP METHOD FOR AUTOMATIC PID PARAMETERS TUNING

A control loop is necessary in order to control a plant or system in order to gain low error system, robust system, or system with fast response depend on the purpose. The most commonly known and used control loop is Proportional-Integral/Proportional-Integral-Derivative. In order to gain the desired output, its parameters, which have different effects, have to be set according to the design requirements. Several methods can be used to determine the parameter; one of them is Ziegler-Nichols closed-loop method. The purpose of this project is to carry out FPGA implementation of Ziegler-Nichols closed-loop method for automatic PID parameters tuning. The commonly used design hardware for digital projects is microcontroller. Microcontroller device resources is limited, we do not know how much device resources this project will take, and to add an additional resources is quite complicated as well, therefore we choose FPGA instead. This project is part of a bigger project which consists of three projects, which are handled by a student each. The most important parts for this project are estimator and controller modules which are located in the FPGA. This is because the estimator’s function is to do the steps of the Ziegler-Nichols closed loop method and the controller is necessary because the estimator cannot function if there is no controller. To build and test out the system, it is necessary to begin from the subsystems. If the subsystem’s tests are successful, then the probability for the overall system to be success is higher. Experimental results show that the subsystems have been successfully designed, but the overall system could not be applied because the target Spartan 3E FPGA does not have sufficient logic resources on. The first and second objectives was achieved but the third objective was not achieved because this project could not be applied on the target FPGA and therefore this project has not been used on the real tools.Keywords – Auto-tuning PID controller, Ziegler-Nichols, FPGA Implementatio

Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D

Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre dans l'industrie. Sur la base des listes d'interconnexions en déroute, nous procédons à l'analyse des performances d'évaluer le bénéfice de l'architecture 3D par rapport à sa mise en oeuvre 2D. Sur la base du flot de conception 3D proposé en se concentrant sur la vérification temporelle tirant parti de l'avantage du retard négligeable de la structure de microbilles pour les connexions verticales, nous avons mené techniques de partitionnement de NoC 3D basé sur l'architecture MPSoC y compris empilement homogène et hétérogène en utilisant Tezzaron 3D IC technlogy. Conception et mise en oeuvre de compromis dans les deux méthodes de partitionnement est étudiée pour avoir un meilleur aperçu sur l'architecture 3D de sorte qu'il peut être exploitée pour des performances optimales. En utilisant l'approche 3D homogène empilage, NoC topologies est explorée afin d'identifier la meilleure topologie entre la topologie 2D et 3D pour la mise en œuvre MPSoC 3D sous l'hypothèse que les chemins critiques est fondée sur les liens inter-routeur. Les explorations architecturales ont également examiné les différentes technologies de traitement. mettant en évidence l'effet de la technologie des procédés à la performance d'architecture 3D en particulier pour l'interconnexion dominant du design. En outre, nous avons effectué hétérogène 3D d'empilage pour la mise en oeuvre MPSoC avec l'approche GALS de style et présenté plusieurs analyses de conception physiques connexes concernant la conception 3D et la mise en œuvre MPSoC utilisant des outils de CAO 2D. Une analyse plus approfondie de l'effet microbilles pas à la performance de l'architecture 3D à l'aide face-à-face d'empilement est également signalé l'identification des problèmes et des limitations à prendre en considération pendant le processus de conception.In this thesis, we study the exploration 3D NoC architectures through physical design implementations using real 3D technology used in the industry. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Keberkesanan program keusahawanan dan transformasi nelayan di Pulau Langkawi, Kedah

Malaysian government had long been focusing in driving the economic transformation agenda for coastal fishing community due to the uncertain income generation and the inability to improve their economic levels above their subsistence needs. Although various fisherman development programmes had been implemented, it was found that did not have the impact that could change their livelihood. This study was able to explain the problems faced by fishermen in Langkawi Island who had joined Zone A Fishermen’s Income Increase Programme (cage culture farming). Therefore, the objectives of this study were to identify the problems faced by the participants joining this programme, to analyse the effectiveness of the programme, and to determine the changes in income generation of the participants. This study was done quantitatively and had involved a total of 30 respondents consisting the fishermen who had participated in the programme and sampled through stratified sampling. A pilot study has been carried out to make sure that the respondents understood the given questions well. The data was obtained through interview method and tested using descriptive test to get the demographic distribution of respondents. The findings show that there are three variables (income gained; savings; programme effects) which are found to affect the economic change of participants after participating in the programme, seven variables (input assistances; revolving capital; water quality; lack of skills; participant relationship; motivation; advisory services) are found to affect the implementation of the programme and four variables (aquaculture activities; adequate aquaculture input; economic level; programme affects) are found to affect the effectiveness of the fisherman’s improvement programme. The findings of the study show that the fishing community should be prepared and need to strive to improve themselves so that their lives will improve. The government should also play an important role in helping the fishing community to increase their income. Therefore, the improvement of more planned and controlled programmes need to be suggested so that each of the programme will be more effective and gives a positive impact especially to the target group

Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power

The static power consumption is an important parameter concern in IC design due to t for a higher integration numbers of transistor to achieve greater performance in a single chip. Leakage current is the main issues for static power dissipation in standby mode as the size of transistor been scale. Therefore, the subthreshold leakage current rises due to threshold voltage scaling and gate leakage current increases due to scale down of oxide thickness. In this paper, a Variable Body Biasing (VBB) technique was applied to reduce static power consumption in VLSI design. The VBB technique used a DC bias at body terminal to control the threshold voltage efficiently. The Synopsys Custom Designer EDA tools in 90nm MOSFET technology was used to design a 1-bit full adder with VBB technique in full custom methodology. The simulation of 1-bit full adder was carried out with operation voltage   supply was compared in conventional technique and VBB technique. The results achieved the reduction in term of peak power,   and average power,   in static CMOS 1-bit full adder compared with conventional bias and VBB technique

Microwave characterization of bio-composites materials based finite element and Nicholson-Ross-Weir methods

In this work, Bio-composite of oil palm empty fruit bunch fibre (OPEFB)-filler and polycaprolactone (PCL)-polymer has been prepared and characterized. The functional groups and morphology of the prepared samples were characterized by Fourier transform infrared spectroscopy (FT-IR). By using the Nicholson- Ross-Weir (NRW) mode, both of real and imaginary relative permittivity values of the samples were obtained simultaneously from the reflection and transmission coefficient measurements of the materials. Whereas, the attenuation with the field distribution at the waveguide filled with a sample were considered by using the Finite Element Method (FEM). The magnitude of the reflection and transmission (R/T) coefficients of the composite with different filler percentages were measured using rectangular waveguide in conjunction with a microwave vector network analyzer (VNA) in X-band range of frequency. The computations of the S-parameters were achieved by using the FEM technique along with NRW mode. Then, the obtained results were compared with the measured R/T coefficients. Relative error results nominated the FEM mode due to its highly accurate results than the other method

Web-based reward and redemption system for smart recyle system

The Recycling rate among developing nation is very low and the number of waste is increasing every day.Although many steps have been taken such as through national campaign, yet the recycle rate remains unchanged especially in Malaysia.Thus, the smart recycle bin is proposed to give a reward to public user who thrown the recyclable waste into the innovated smart recycle bin by giving points (later can be converted to money).This paper discussed the development of reward-based smart recycle system.The system has been implemented in a web-based environment and it supports for public user and waste authority.The system is then to be integrated with the desktop-based applications for waste authority to manage the point and transaction from the innovated recycle bin to the reward system